1. Field of the Invention
This invention relates generally to the field of digital data processing systems, and more specifically to a central processing unit for connection in data processing systems having system buses with diverse characteristics.
2. Description of the Prior Art
A digital data processing system generally includes three basic elements: a memory element, an input/output element, and a processor element connected by one or more buses. The memory element stores information in addressable storage locations. This information includes both data and instructions for processing the data. The processor element causes information to be transferred between it and the memory element, interprets the incoming information as either data or instructions, and processes the data in accordance with the instructions. An input/output element also communicates with the memory element in order to transfer information into the system and to obtain the processed information from it. The input/output elements normally operate in accordance with control information supplied to it by the processor element. The input/output elements may include operator consoles, printers or teletypewriters, or may also include secondary memory storage units such as disk drives or tape drives.
A data processing system may be designed to transfer information over one system bus to which all of the elements are connected. The system bus itself is designed to have certain predetermined logical and electrical characteristics. The signal paths for transferring information signals and for transferring control signals that control the operation of the elements in respect of the information signals are logical factors that determine the bus' logical characteristics. The components selected to be used in the physical implementation of the system determine the electrical characteristics. While the electrical characteristics of the components are reasonably standardized, the logical characteristics are not standardized, but are generally determined by the system design.
A processor is typically designed to operate in a data processing system having particular logical bus characteristics. These characteristics determine, inter alia, whether a bus has signal paths for transferring either one byte, multiple bytes in parallel, what bus control signals occur at particular times, the maximum number of addressable storage locations that may be provided in the memory, and the sequence in which address signals are provided, and whether timing signals define timing cycles of a particular duration.
For example, in a data processing system having a bus with signal paths for transferring single bytes of information in parallel to and from a memory, it would be necessary to develop complex arrangements to facilitate transfer by a processor designed to operate in a system in which a word comprising two bytes was transferred in parallel. These arrangements would include circuitry for arranging the separate bytes of each word in memory. Alternatively, the processor could ignore one of the bytes of each word during processing if only one information byte is transferred in parallel, but this could be wasteful in a processor designed to operate on words of information.
As another example, the maximum size of the memory element determines the number of address bits required to physically address a particular storage location. A memory element having 65,536 separately addressable storage locations (typically referred to as a "64K" memory) requires sixteen address bits, whereas a memory having as many as 32,768 separately addressable storage locations (a "32K" memory) requires only fifteen address bits. A processor designed to work in a system having at most a 32K memory thus will not work with a 64K memory without some type of memory address extension mechanism.
Similarly, different memory elements may require address signals to be provided in different patterns. Some memory elements must receive all of the address bits simultaneously, whereas other memories may require the bits to be divided into portions denominated row address bits and column address bits, and transferred sequentially. The former arrangement is typically a characteristic of a static memory, whereas the latter arrangement is typically a characteristic of a dynamic memory. Another difference between the static and dynamic memories is that the contents of the storage locations of dynamic memories may decay over time, whereas those of static memories do not. To prevent the loss of the contents of the dynamic memory's storage locations, refreshing operations are performed in the system. Such refreshing operations may be initiated by the memory itself, however, often they are initiated by the processor.
Different data processing systems also define the timing of certain bus control signals, for example, a transfer direction, or "read/write", control signal. Some systems require the read/write control signal to be provided simultaneously with the address. Others require the read/write control signal to be provided only after the address signals are transferred. Normally, a processor does not provide such control signals having both timings.
The various elements of data processing system are often designed to operate in response to internal timing signals that have a particular relationship to timing signals that are generated in the system and transferred over the bus. For example, in some data processing systems timing signals generated by the processor control all the timing in the system. In other data processing systems, a timing standard that is external to the processor produces timing signals that the processor and other elements receive and convert to their internal timing signals.
Finally, a processor, particularly a processor designed to operate with a synchronous bus, is usually designed to operate with a characteristic timing interval or cycle having a particular maximum duration. In a synchronous bus, the signals transferred over the bus have a particular relationship to certain timing signals that define the timing intervals or cycles. The duration of the timing signals or intervals is normally determined to reflect the speed with which a memory element included in the system can normally transfer information to or retrieve information from an addressed location. Typically a processor having a long internal timing cycle is not connected in a system having faster memories, because such memories are usually more expensive than the slower memories, and a faster memory is not required in a system having such a long internal timing cycle. On the other hand, a processor having a short internal timing cycle would not normally be connected to a memory requiring longer timing cycles without significant modification.